Pixels on a flat panel display generally correspond to the intersection of source lines (typically corresponding to columns of a matrix) and gate lines (typically corresponding to rows of the matrix). As display formats tend to increase in size, the rate of the data that must be transferred to the display must be increased accordingly. For example, using the same clock frequency, an ultra extended graphics array (UXGA) (having 1600 columns by 1200 rows, i.e., 1600×1200) requires four times the rate of data transfer as the super video graphics array (SVGA) format (800×600). In practical terms, this could mean that the UXGA could require four times as many data lines in its interface bus as does the SVGA. But if the number of data lines for each interface bus is to be kept the same, then the UXGA interface bus has to operate at a frequency four times greater than the interface bus of the SVGA.
Another tendency in the display art is for the bit length of the gray scale to increase. Formerly, 18-bit gray scale schemes were common. Twenty-four bit gray scale schemes seem likely to replace the 18-bit schemes. And it is likely that increasingly lengthier bit schemes will be adopted. The 24-bit scheme uses 8-bits for the red, blue and green colors. The 18-bit scheme uses 6-bits for each color, i.e., R, G and B. The change in gray-scale bit length from 18 to 24 represents an increase in data rate by approximately 33%.
FIG. 1 depicts a schematic block diagram of a flat panel display system 100 according to the Background Art. This system 100 has a graphic controller 102 that includes a low voltage differential signal (LVDS) transmitter (TX) 104. The system 100 further has a flat panel display device, e.g., a liquid crystal display (LCD) device, 106 that includes: a timing controller 108; source driver circuits 110; gate driver circuits 112; and a thin film transistor (TFT) LCD panel 114. The graphic controller 102 provides display signals to the timing controller 108 via the LVDS TX 104. The timing controller 108 provides corresponding data signals to the source driver circuits 110 and the gate driver circuits 112.
A first type of technology for implementing the interface bus of the LCD device 106 is based on transistor-transistor logic (TTL). FIG. 2A depicts a simple schematic block diagram of a TTL display system 200 according to the Background Art. The system 200 includes: a timing controller (T_CON) 202 that itself includes a transmitter 204; a transmission line 206; and a source driver 208 that itself includes a receiver 210. FIG. 2A has been simplified by depicting only one transmitter 204, one transmission line 206 and one receiver 210; in actuality a plurality of each would be present. FIG. 2B depicts a more detailed schematic block diagram of the TTL display system 200. FIG. 2B includes an LVDS transmitter 212 and an LCD device 214. The LCD device 214 includes a timing controller 216 that itself includes an LVDS receiver (RX) 218, a phase-locked-loop (PLL) 219 and a TTL TX 220. The LCD device 214 further includes a plurality of source drivers 2081, 2082 . . . 2088.
FIG. 2B assumes a 6-bit gray scale scheme. As such, each pixel's worth of data received by the LVDS TX 212 represents a total of 18-bits, i.e., 6bits for each of the R, G and B colors. Basic TEL technology can operate at a clock speed of up to approximately 40 MHz. This clock speed is sufficient for the SVGA format (800×600), but is insufficient for the Extended Graphics Array (XGA) format (1024×768). The Background Art adapted the TEL technology to the higher XGA-level resolution by using frequency division. In other words, the timing controller 216 of FIG. 2B receives display data at a rate of 65 MHz via the LVDS receiver 218, which transfers it to the TEL transmitter 220. The TEL transmitter 220 provides the data to the respective source drivers 208 via two transmission lines, 206A and 206B, connected to each of the source drivers 208. Each of the transmission lines 206A and 206B operate at 32.5 MHz, i.e., half of the input data rate of 65 MHz.
But there are problems with this higher speed TTL arrangement. First, the number of data lines is doubled where, as in FIG. 2B, the frequency is halved. This increases the number of timing controller output pins and column driver input pins, which increases the surface area of the printed circuit board (PCB), increases cost and makes it much more difficult to achieve a compact design.
In addition, as the density of the interconnections on the PCB increases, such wiring is more prone to timing errors due to interference between the signal lines. FIGS. 2C and 2D depict the electric field and magnetic field radiation patterns from a TTL transmission line 206, respectively. In addition, each of the transmission lines 206 itself is easily affected by external noise. To reduce the noise contributed by the transmission lines 206, filters (not depicted) can be inserted into the transmission lines 206, but this further increases the surface area of the PCB that is consumed and further reduces the timing margin.
To solve some of the problems of a TTL-based bus interface, a reduced swing differential signaling (RSDS) bus interface was adopted by the Background Art. FIG. 3A depicts a simplified schematic block diagram of an RSDS bus interface system 300. The system 300 includes a transmission controller 302 (that includes its own transmitter 304), paired transmission lines 306A and 306B, a terminating resistor 311 and a source driver 308 (that includes its own receiver 310).
FIG. 3B is a more detailed version of the RSDS interface bus of FIG. 3A. In particular, FIG. 3B includes an LVDS transmitter (TX) 312 that provides display data to an LCD device 314. The LCD device 314 includes a timing controller 302 and source drivers 322. The timing controller 302 includes an LVDS receiver (RX) 318 and an RSDS TX 320.
As in FIG. 2B, a 6-bit gray scale scheme is assumed for FIG. 3B. RGB data totaling 18-bits per pixel is supplied to the LVDS transmitter 312 at 65 MHz. This data is transferred from the LVDS transmitter 312 to the LVDS receiver 318, which transfers the data then to the RSDS transmitter 320. Unlike the TTL-based technology of FIG. 2B, the RSDS-based technology of FIG. 3B can provide data from the RSDS transmitter 320 to each of the source drivers 322 at 65 MHz using 9 pairs of lines 306A, 306B. The system 300 conforms to the XGA mode, so 1024 pixel columns must be accommodated. Using RGB technology, each column is supplied with three color values R, G and B. In the example of FIG. 3B, eight source drivers 322 have been provided. As a result, each source driver 322 drives 384 columns or channels (1024×3/8).
The RSDS bus interface is based upon the concept of a current loop. A signal corresponding to a voltage difference across the terminating resistor 311 is used to convey whether the corresponding logical level is one or zero. The current flowing in each of transmission lines 306A and 306B is correspondingly less than in the transmission line 206 of FIG. 2A. Consequently, the RSDS bus interface produces a lower level of electromagnetic interference (EMI). FIGS. 3D and 3E depict the electric field and the magnetic field, respectively, associated with the transmission line pair 306A and 306B of the RSDS interface bus.
FIG. 3D depicts the sensing circuitry of FIG. 3A in more detail. In FIG. 3D, the terminating resistor 311 is represented as a series connection of two resistance values Rzo, equaling a total resistance of 2 Rzo. The receiver 310 in FIG. 3D is a comparator whose non-inverting input is connected ahead of the terminating resistor 311 (i.e., to transmission line 306A) and whose inverting input is connected after the terminating resistor 311 (i.e., to transmission line 306B). It should be noted that the terminating resistor 311 is external to the source driver 308. Stated differently, the RSDS bus interface is a current sourcing and current sensing scheme.
In the RSDS technique, the amplitude of a signal on the transmission lines 306A and 306B is reduced to 0.2 volts, which is much less than the typical TTL amplitude of 3.3 volts. Again, this is because the relative difference between the voltage levels on transmission lines 306A and 306B conveys the information content in the RSDS scheme. The RSDS paired transmission line arrangement produces less EMI than the single transmission line of the TTL arrangement. Also, the much smaller signal level used in the RSDS scheme results in a data bus having a smaller width than the TTL scheme, which leads to a reduction in the amount of the PCB surface area that is consumed.
But a disadvantage of the RSDS scheme is that each datum requires a pair of transmission lines 306A and 306B, which significantly increases the consumption of PCB surface area. Also, the pairs of transmission lines 306A and 306B requires the presence of external terminating resistors 311, which also increases the consumption of PCB surface area. Lastly, the RSDS technique is limited to a maximum clock speed of about 100 MHz. This precludes the RSDS technique from being used with a higher resolution display format that necessarily requires a faster data rate.
Because of the limitations in the RSDS bus interface, the Background Art adopted the Whisper Bus type of bus interface. FIG. 4A depicts a simplified schematic block diagram of the Whisper Bus system 400 according to the Background Art. The system 400 includes a timing controller 402 (which has a transmitter 404), a transmission line 406 and a source driver 408 (which has a receiver 410).
FIG. 4B depicts the Background Art Whisper Bus interface system of FIG. 4A in more detail as including an LVDS transmitter 412 and an LCD device 414. The LCD device 414 includes a timing controller 416 and source drivers 422. The timing controller 416 includes an LVDS receiver 418 and a whisper transmitter 420. The transmitter 412 receives 18 bits of RGB display data per pixel and provides that data to the timing controller 416 via the receiver 418 at a data rate of 65 MHz. The receiver 418 transfers the data to the whisper transmitter 420 at a rate of 65 MHz. The whisper transmitter 420 then provides the display data to the source drivers 422 at a rate of 73.125 MHz.
Like the TTL arrangements of FIGS. 2A and 2B, the Whisper Bus arrangement of FIGS. 4A and 4B uses only one transmission line per datum, which contrasts with the two transmission lines per datum used in the RSDS arrangement of FIGS. 3A and 3B. Unlike the TTL arrangement of FIGS. 2A and 2B, the Whisper Bus arrangement of FIGS. 4A and 4B reduces the current on the transmission line 406 from the 2 mA level of the TTL technology down to 300μA. Consequently, the Whisper Bus technology produces low amounts of EMI and consumes small amounts of power. Plus, in contrast to the RSDS technology, the Whisper Bus arrangement uses half the number of transmission lines. In other words, where the RSDS technology requires 2N transmission lines, only N data transmission lines are required for the Whisper Bus technology.
A further difference between the Whisper Bus technology and the RSDS technology concerns the external terminating resistor of the RSDS technology. Again, the terminating resistor 311 is outside the integrated circuit of the receiver 310. FIG. 4C shows that the receiver 410 is implemented by a comparator (as the receiver 410) whose inverting input is connected to the transmission line 406 via a serially-connected terminating resistor 425 that is internal to the integrated circuit of the source driver 408. The terminating resistor 425 can be an active resistance formed of transistors. The non-inverting input of the comparator 410 is connected to a reference voltage source 430. In addition, a feedback resistance 420 is connected between the output of the comparator 410 and the inverting input.
The Whisper Bus technology achieves high data rates, a reduced bus width and significantly reduced current levels, in contrast to the RSDS technology. But, the single transmission line arrangement of the Whisper Bus technology remains quite vulnerable to external noise.